HDL Works offers you a solution to translate FLDL-E (The Extended Fujitsu Logic Description Language) and FTDL-E (The Extended Fujitsu Test data Description Language) to VHDL.
HDL Works developed sofware that is able to translate the FLDL netlist and most of the FTDL automatically. The resulting VHDL netlist in combination with the technology library is synthesizable with all major synthesis tools. The FTDL testvectors are translated into VHDL and should pass in any simulator to ensure correctness of the translated netlist and technolgy library. Several Fujitsu ASICs have been succesfully converted into FPGAs by Thales Naval Systems using this translator.
The translation is available both as a software program and as a service.
Output of the translation
- VHDL design file
- VHDL testbench file containing:
- Testbench entity
- Architecture for each test present
- Vector file(s), one for each test present
- TCL script file to:
- Create libraries work and ftdl
- Compile the ftdl_reader_pkg package file
- Compile the VHDL entity file and testbench file.
- Run simulation for each test.
The following technologies libraries are available:
Other libraries can be created on demand.
- Design reuse of existing FLDL designs in VHDL
- Single design and test environment for your project
- Automated translation prevents errors made during manual translation
- Translation in seconds instead of days
The following (test) constructs described by the keywords below in the FTDL language are currently not supported.
- RAM – ENDRAM
- MEASURE – ENDMEAS
- WAVE – ENDWAVE
For more information or a quote on the translation of your FLDL/FTDL to VHDL (or Verilog) please contact HDL Works firstname.lastname@example.org.